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st ST8011 120 output lcd segment driver ic notice: sitronix technology corp. reserves the right to change the contents in this document without prior notice. this is not a final specification. some parameters are subject to change v1.3 1/ 20 2004/09/08 n description the ST8011 is a 120-output segment driver ic suitable for driving small/medium scale dot matrix lcd panels, and is used in pda or electronic dictionary . the ST8011 is good as a segment driver, and it can create a low power consuming, high-resolution lcd. n features ? number of lcd drive outputs: 120 ? supply voltage for lcd drive: max +16v ? supply voltage for the logic system: +2.5 to +5.5 v ? low power consumption ? package: 136-pin cob. (segment mode) ? shift clock frequency - 20 mhz (max.): v dd = +5.0 0.5 v - 15 mhz (max.): v dd = +3.0 to + 4.5 v - 12 mhz (max.): v dd = +2.5 to + 3.0 v ? adopts a data bus system ? 4-bit parallel / serial input modes are selectable with a mode (p/s) pin ? automatic transfer function of an enable signal ? automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 120 bits of input data ? line latch circuits are reset when xdispoff active
ST8011 v1.3 2/20 2004/09/08 n ST8011 serial specification revision history ST8011 serial specification revision history version date description 0.0b 2002/10/14 preliminary version 1.0 2003/07/28 final version 1.1 2003/11/12 modify the pin pitch 1.2 2004/04/05 add application timing block diagram 1.3 2004/09/08 define timing( t lsw ) of segment mode. p17~p19
ST8011 v1.3 3/20 2004/09/08 n pad arrangement chip size: 4860( m) 2220( m) pad size: 80( m) 80( m) pin pitch: 100~110 m s eg1 04 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 0 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 8 6 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 3 6 1 3 5 s t 8 0 1 1 se g10 5 seg 106 s eg1 07 se g10 8 seg 109 s eg1 10 se g11 1 seg 112 se g1 13 se g11 4 s eg 115 se g11 6 seg 117 s eg1 18 se g11 9 v0 v 2 v3 di3 d i2 di1 d i0 ei o1 eio 2 x ck fr lp v dd xd isp off p s v ss seg 0 s eg1 se g2 seg 3 s eg4 se g5 seg 6 se g7 seg 8 s eg9 se g10 seg 11 s eg1 2 se g13 seg 14 seg15 s e g 1 6 s e g 1 7 s e g 1 8 s e g 1 9 s e g 2 0 s e g 2 1 s e g 2 2 s e g 2 3 s e g 2 4 s e g 2 5 s e g 2 6 s e g 2 7 s e g 2 8 s e g 2 9 s e g 3 0 s e g 3 1 s e g 3 2 s e g 3 3 s e g 3 4 s e g 3 5 s e g 3 6 se g41 seg 40 s eg3 9 se g38 seg 37 se g46 seg 45 se g4 4 seg 43 s eg4 2 seg 51 s eg5 0 se g49 seg 48 s eg4 7 seg 56 s eg5 5 se g54 s eg 53 se g52 s eg6 1 se g60 seg 59 s eg5 8 se g57 s eg6 6 se g65 seg 64 se g6 3 seg 62 se g71 seg 70 s eg6 9 se g68 seg 67 se g76 seg 75 s eg7 4 se g73 s eg 72 seg 81 s eg8 0 se g79 seg 78 s eg7 7 se g82 s e g 1 0 3 s e g 1 0 2 s e g 1 0 1 s e g 1 0 0 s e g 9 9 s e g 9 8 s e g 9 7 s e g 9 6 s e g 9 5 s e g 9 4 s e g 9 3 s e g 9 2 s e g 9 1 s e g 9 0 s e g 8 9 s e g 8 8 s e g 8 7 s e g 8 6 s e g 8 5 s e g 8 4 s e g 8 3 l / r l / r substrate connect to vss. pin1
ST8011 v1.3 4/20 2004/09/08 pad location coordinates pad.no function x y pad.no function x y 1 seg104 2385.00 1065.00 69 seg36 - 2385.00 - 1065.00 2 seg105 2265.00 1065.00 70 seg37 - 2265.00 - 1065.00 3 seg106 2155.00 1065.00 71 seg38 - 2155.00 - 1065.00 4 seg107 2050.00 1065.00 72 seg39 - 2050.00 - 1065.00 5 seg108 1950.00 1065.00 73 seg40 - 1950.00 - 1065.00 6 seg109 1850.00 1065.00 74 seg41 - 1850.00 - 1065.00 7 seg110 1750.00 1065.00 75 seg42 - 1750.00 - 1065.00 8 seg111 1650.00 1065.00 76 seg43 - 1650.00 - 1065.00 9 seg112 1550.00 1065.00 77 seg44 - 1550.00 - 1065.00 10 seg113 1450.00 1065.00 78 seg45 - 1450.00 - 1065.00 11 seg114 1350.00 1065.00 79 seg46 - 1350.00 - 1065.00 12 seg115 1250.00 1065.00 80 seg47 - 1250.00 - 1065.00 13 seg116 1150.00 1065.00 81 seg48 - 1150.00 -10 65.00 14 seg117 1050.00 1065.00 82 seg49 - 1050.00 - 1065.00 15 seg118 950.00 1065.00 83 seg50 - 950.00 - 1065.00 16 seg119 850.00 1065.00 84 seg51 - 850.00 - 1065.00 17 v0 750.00 1065.00 85 seg52 - 750.00 - 1065.00 18 v2 650.00 1065.00 86 seg53 - 650.00 - 1065.00 19 v3 550.00 1065.00 87 seg54 - 550.00 - 1065.00 20 di3 450.00 1065.00 88 seg55 - 450.00 - 1065.00 21 di2 350.00 1065.00 89 seg56 - 350.00 - 1065.00 22 di1 250.00 1065.00 90 seg57 - 250.00 - 1065.00 23 di0 150 .00 1065.00 91 seg58 - 150.00 - 1065.00 24 eio1 50.00 1065.00 92 seg59 - 50.00 - 1065.00 25 eio2 - 50.00 1065.00 93 seg60 50.00 - 1065.00 26 xck - 150.00 1065.00 94 seg61 150.00 - 1065.00 27 fr - 250.00 1065.00 95 seg62 250.00 - 1065.00 28 lp - 350.00 1065.00 96 seg63 350.00 - 1065.00 29 vdd - 450.00 1065.00 97 seg64 450.00 - 1065.00 30 xdispoff - 550.00 1065.00 98 seg65 550.00 - 1065.00 31 ps - 650.00 1065.00 99 seg66 650.00 - 1065.00 32 vss - 750.00 1065.00 100 seg67 750.00 - 1065.00 33 seg0 - 850.00 1065.00 101 seg68 850.00 - 1065.00 34 seg1 - 950.00 1065.00 102 seg69 950.00 - 1065.00 35 seg2 - 1050.00 1065.00 103 seg70 1050.00 - 1065.00 36 seg3 - 1150.00 1065.00 104 seg71 1150.00 - 1065.00 37 seg4 - 1250.00 1065.00 105 seg72 1250.00 - 1065.00
ST8011 v1.3 5/20 2004/09/08 pad.no function x y pad.no function x y 38 seg5 - 1350.00 1065.00 106 seg73 1350.00 - 1065.00 39 seg6 - 1450.00 1065.00 107 seg74 1450.00 - 1065.00 40 seg7 - 1550.00 1065.00 108 seg75 1550.00 -1 065.00 41 seg8 - 1650.00 1065.00 109 seg76 1650.00 - 1065.00 42 seg9 - 1750.00 1065.00 110 seg77 1750.00 - 1065.00 43 seg10 - 1850.00 1065.00 111 seg78 1850.00 - 1065.00 44 seg11 - 1950.00 1065.00 112 seg79 1950.00 - 1065.00 45 seg12 -205 0.00 1065.00 113 seg80 2050.00 - 1065.00 46 seg13 - 2155.00 1065.00 114 seg81 2155.00 - 1065.00 47 seg14 - 2265.00 1065.00 115 seg82 2265.00 - 1065.00 48 seg15 - 2385.00 1065.00 116 seg83 2385.00 - 1065.00 49 seg16 - 2385.00 955.00 117 seg84 2385.00 - 955.00 50 seg17 - 2385.00 850.00 118 seg85 2385.00 - 850.00 51 seg18 - 2385.00 750.00 119 seg86 2385.00 - 750.00 52 seg19 - 2385.00 650.00 120 seg87 2385.00 - 650.00 53 seg20 - 2385.00 550.00 121 seg88 2385.00 - 550.00 54 seg21 - 2385.00 450.00 122 seg89 2385.00 - 450.00 55 seg22 - 2385.00 350.00 123 seg90 2385.00 - 350.00 56 seg23 - 2385.00 250.00 124 seg91 2385.00 - 250.00 57 seg24 - 2385.00 150.00 125 seg92 2385.00 - 150.00 58 seg25 - 2385.00 50.00 126 seg93 2385.00 - 50.00 59 seg26 - 2385.00 - 50.00 127 seg94 2385.00 50.00 60 seg27 - 2385.00 - 150.00 128 seg95 2385.00 150.00 61 seg28 - 2385.00 - 250.00 129 seg96 2385.00 250.00 62 seg29 - 2385.00 - 350.00 130 seg97 2385.00 350.00 63 seg30 - 2385.00 - 450.00 131 seg98 2385.00 450.00 64 seg31 - 2385.00 - 550.00 132 seg99 2385.00 550.00 65 seg32 - 2385.00 - 650.00 133 seg100 2385.00 650.00 66 seg33 - 2385.00 - 750.00 134 seg101 2385.00 750.00 67 seg34 - 2385.00 - 850.00 135 seg102 2385.00 850.00 68 seg35 - 2385.00 - 955.00 136 seg103 2385.00 955.00
ST8011 v1.3 6/20 2004/09/08 pin description symbol i/o description no of num seg0-seg119 o lcd drive output 120 v0,v2,v3 p power supply for lcd drive 3 xdispoff i control input for output of non-select level 1 vdd p power supply for logic system (+2.5 to +5.5 v) 1 eio2, eio1 i/o input/output for chip selection at segment mode and flm input output function at com/seg mix mode or common mode 2 di0-di3 i display data input at segment mode 4 xck i clock input for taking display data at segment mode 1 l/r i display data shift direction selection lp i latch pulse input for display data at segment mode/ shift clock input for shift register at common mode 1 fr i ac-converting signal input for lcd drive waveform 1 p/s i this is the parallel data input/serial data input switch terminal. p/s= h : parallel data input. p/s= l : serial data input. 1 vss p ground (0 v) 1 n block diagram
ST8011 v1.3 7/20 2004/09/08 n input/output circuits i v dd to internal circuit vss (0v) applicable pins xdispoff , di 3 ~di 0 , lp , fr , p/s,l/r input circuit v dd i/o to internal circuit vss (0v) vss (0v) control signal vss (0v) v dd output signal control signal application pins eio 1 , eio 2 input/output circuit
ST8011 v1.3 8/20 2004/09/08 n functional description u pin functions symbol function vdd logic system power supply pin, connected to +2.5 to +5.5 v. vss ground pin, connected to 0 v. v0 v2 v3 this is a multi-level power supply for the liquid crystal drive. the voltage supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. voltage levels are determined based on vss, and must maintain the relative magnitudes shown below. ? v0 v2 v3vss RRR di3-di0 input pins for display data ? in 4-bit parallel input mode, input data into the 4 pins, di3-di0. ? in serial input mode, input data into the 1 pin di0. connect di3-di1 to vss or vdd ? refer to "relationship between the display data and lcd drive output pins" in functional operations. xck clock input pin for taking display data * data is read at the falling edge of the clock pulse. lp latch pulse input pin for display data ? data is latched at the falling edge of the clock pulse. xdispoff control input pin for output of non-select level ? the input signal is level- shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? when set to vss level "l", the lcd drive output pins (seg0-seg119) are set to level vss. ? when set to "l", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /dispoff. when the xdispoff function is canceled, the driver outputs non-select level (v2 or v3), then outputs the contents of the data latch at the next falling edge of the lp. at that time, if x dispoff removal time does not correspond to what is shown in ac characteristics, it cannot output the reading data correctly. ? table of truth-values is shown in "truth table" in functional operations. fr ac signal input pin for lcd drive waveform ? the input signal is level- shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? normally it inputs a frame inversion signal. ? the lcd drive output pins' output voltage levels can be set using the line latch output signal and the fr signal. ? table of truth-values is shown in "truth table" in functional operations. p/s interface mode selection pin ? when p/s is h then parallel data input mode.
ST8011 v1.3 9/20 2004/09/08 when p/s is l the serial data input mode, l/r input pin for selecting the reading direction of display data. default value is low ? when set to v ss level "l", data is read sequentially from seg 119 to seg 0 . ? when set to v dd level "h", data is read sequentially from seg 0 to seg 119 . ? refer to "relationship between the display data and lcd drive output pins" in functional operations. elo1, eio2 input/output pins for chip selection. at segment mode: ? when l/r input is at vss level "l", elo1 is set for output, and eio2 is set for input(connect to vss). ? when l/r input is at vdd level "h", elo1 is set for input(connect to vss), and eio2 is set for output. ? during output, set to "h" while lp ? xck is "h" and after 120 bits of data have been read, set to "l for one cycle (from falling edge to failing edge of xck), after which it returns to "h". during input, the chip is selected while el is set to "l" after the lp signal is input. the chip is non-selected after 120 bits of data have been read. seg0 C seg119 lcd drive output pins ? corresponding directly to each bit of the data latch, one level (v0, v2, v3, and vss) is selected and output. ? table of truth values is shown in "truth table" in functional operations. u functional operations fr latch data /dispoff lcd drive output voltage level (seg0-seg119) l l h v3 l h h vss h l h v2 h h h v0 x x l vss truth table notes: ? l : vss (0 v), h : vdd (+2.5 to +5.5 v), ? "don't care" should be fixed to "h" or "l", avoiding floating. there are two kinds of power supply (logic level voltage and lcd drive voltage) for the lcd driver. supply regular voltage that is assigned by specification for each power pin.
ST8011 v1.3 10/20 2004/09/08 u relationship between the display data and lcd drive output pins (a) 4-bit parallel input mode number of clocks l/r eio1 eio2 data input 30 clock 29 clock 28 clock 3 clock 2 clock 1 clock di 0 seg 0 seg 4 seg 8 seg 108 seg 112 seg 116 dl 1 seg 1 seg 5 seg 9 seg 109 seg 113 seg 117 di 2 seg 2 seg 6 seg 10 seg 110 seg 114 seg 118 l output input di 3 seg 3 seg 7 seg 11 seg 111 seg 115 seg 119 di 0 seg 119 seg 115 seg 111 seg 11 seg 7 seg 3 dl 1 seg 118 seg 114 seg 110 seg 10 seg 6 seg 2 di 2 seg 117 seg 113 seg 109 seg 9 seg 5 seg 1 h input output di 3 seg 116 seg 112 seg 108 seg 8 seg 4 seg 0 (b) serial input mode number of clocks l/r eio1 eio2 data input 120 clock 119 clock 118 clock di0 seg0 seg1 seg2 seg117 seg118 seg119 dl1 x x x x x x x di2 x x x x x x x l output input di3 x x x x x x x di0 seg119 seg118 seg117 seg2 seg1 seg0 dl1 x x x x x x x di2 x x x x x x x h input output di3 x x x x x x x notes: ? l : vss (0 v), h : vdd (+2.5 to +5.5 v), x : don't care "don't care" should be fixed to "h" or "l", avoiding floating.
ST8011 v1.3 11/20 2004/09/08 u connection examples of plural segment drivers (a) when l/r = l (b) when l/r = h seg 0 eio2eio2eio2eio1eio1eio1 xck lp fr di 3 -di 0 x c k l p f r d i 3 - d i 0 l/rl/rl/r v dd 4 top data last data data flow x c k l p f r d i 3 - d i 0 x c k l p f r d i 3 - d i 0 v ss seg 119 seg 0 seg 119 seg 0 seg 119 eio2eio2eio2eio1eio1eio1 xck lp fr di 3 -di 0 x c k l p f r d i 3 - d i 0 x c k l p f r d i 3 - d i 0 x c k l p f r d i 3 - d i 0 l/rl/rl/r v ss 4 top datalast data data flow seg 0 seg 119 seg 0 seg 119 seg 0
ST8011 v1.3 12/20 2004/09/08 u timing chart of 4-device cascade connection of segment drivers n*n*n*n*n*1111122222 device adevice bdevice cdevice d top datalast data *n = 30 in 4-bit parallel input mode *n = 120 in serial input mode eo (device c) eo (device b) eo (device a) ei (device a) di3 - di0 xck lp fr
ST8011 v1.3 13/20 2004/09/08 u precautions precautions when connecting or disconnecting the power supply this ic has a high-voltage lcd driver, so a high current that may flow if voltage is supplied to the lcd drive power supply while the logic system power supply is floating may permanently damage it. the details are as follows, ? when connecting the power supply, connect the lcd drive power after connecting the logic system power. furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the lcd drive power and when connecting the logic power supply, the logic condition of this ic inside is insecure. therefore connect the lcd drive power supply after resetting logic condition of this ic inside on xdispoff function. after that, cancel the xdispoff function after the lcd drive power supply has become stable. furthermore, when disconnecting the power, set the lcd drive output pins to level vss on xdispoff function. then disconnect the logic system power after disconnecting the lcd drive power. when connecting the power supply, follow the recommended sequence shown here v dd v ss v dd v ss v dd v ss v dd xdispoff v 0
ST8011 v1.3 14/20 2004/09/08 application timing block: example 160x80 parallel vs. serial interface diagram s1 s2 s3 s4 s5 s6 s7 s8 s15 s15 s15 s16 1 5 9 13 2 6 10 14 3 7 11 15 4 8 12 16 lp d3 d2 d1 d0 1 2 3 4 5 6 7 8 157 158 159 160 145 149 153 157 146 150 154 158 147 151 155 159 148 152 156 160 1 5 9 2 6 10 3 7 11 4 8 12 d0 1 2 3 4 5 6 7 8 157 158 159 160 frame and lp falling edge (or rising edge) must >10ns between lp falling edge and xck rising edge must >50ns
ST8011 v1.3 15/20 2004/09/08 absolute maximum ratings parameter symbol applicable pins rating unit note supply voltage (1) v dd v dd -0.3~+7.0 v v 2 v 2 v dd -10~ v dd +0.3 v 3 v 3 -0.3~v 5s +10 v input voltage v i d1 4 -di 0 , xck, lp, l/r, fr, eio 1 , eio 2 , xdispoff -0.3 to v dd +0.3 v 1,2 storage temperature t stg -45 to +125 c notes: 1. ta = +25 c 2. the maximum applicable voltage on any pin with respect to v ss (0 v). n recommended operating conditions parameter symbol applicable pins min. typ. max. unit note supply voltage (1) vdd vdd +2.5 +5.5 v supply voltage (2) v0 v0 +6.0 +16.0 v 1, 2 operating temperature topr -20 +85 c notes: 1. the applicable voltage on any pin with respect to v ss (0 v). 2. ensure that voltages are set such that v2 R v3 R vss.
ST8011 v1.3 16/20 2004/09/08 n electrical characteristics u dc characteristics (v ss = 0 v, v dd = +2.5 to +5.5 v, v 0 = + 6.0 to +15.0 v, t opr = -20 to +85 c) parameter symbol conditions applicable pins min. typ. max. unit note input "low" voltage vil 0.2vd d v input "high" voltage vih di3-di0, xck, lp, l/r fr, eio1, eio2, xdispoff 0.8vdd v output "low" voltage vol iol = +0.4 ma +0.4 v output "high" voltage voh ioh = -0.4 ma eio1, eio2 vdd-0.4 v ilil vi = vss -10 a input leakage current ilih vi = vdd di3-di0, xck, lp, lir, fr, eio1, eio2, xdispoff +10 a output resistance ron | ? von| =0.5v v0 = 30 v seg0-seg119 1.5 2.0 k standby current istb vss 50 a 1 supply current (1) (non-selection) iss vss 2.0 ma 2 supply current (2) i0 v0 0.9 ma 4 notes: 1. v dd = +3.0 v, v 0 = +12.0 v 2. v dd = +3.0 v, v 0 = +12.0 v, f xck = 8 mhz, no-load, el = v dd . the input data is turned over by data taking clock (4-bit parallel input mode). 3. v dd = +3.0 v, v 0 = +12.0 v, f xck = 8 mhz, no-load, el = v ss . the input data is turned over by data taking clock (4-bit parallel input mode). 4. v dd = +3.0 v, v 0 = +12.0 v, f xck = 8mhz, f lp = 19.2 khz, f fr = 80 hz, no-load. the input data is turned over by data taking clock (4-bit parallel input mode).
ST8011 v1.3 17/20 2004/09/08 u ac characteristics (v ss = 0 v, v dd = +2.5 to +3.0 v, v 0 = + 6.0 to +15.0 v, t opr = -20 10+85 c) parameter symbol cond iti ons min typ. max. unit note shift clock period t w c k t r , t f w ckh 5 1 ns shift clock "l" pulse width t w ckl 5 1 ns data set up time t ds 30 ns data hold time t dh 40 ns latch pulse "h" pulse width t wlph 5 1 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 5 1 ns latch pulse rise to shift clock rise time t ls 5 1 ns latch pulse fall to shift clock fall time t lh 5 1 ns latch pulse fall to shift clock rise time t lsw 50 ns enable setup time t s 36 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 dispoff removal time t sd 100 ns dispoff "l" pulse width t wdl 1.2 ? d cl = 15 pf 78 n s output delay time (2) t pd 1 , t pd 2 cl = 15 pf 1.2 ? pd 3 cl = 15 pf 1.2 wck - t wckh - t wckl )/2 is maximum in the case of high speed operation. (v ss = 0 v, v dd = +5.0 0.5 v, v 0 = + 6.0 to +15.0 v, t opr = -20 to +85 c) parameter symbol conditions min. typ. max. unit note shift clock period t w c k tr , tf w ckh 23 ns shift clock " l w ckl 23 ns data setup time t ds 15 ns data hold time t dh 23 ns latch pulse "h" pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 50 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns latch pulse fall to shift clock rise time t lsw 50 ns enable setup time t s 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 dispoff removal time t sd 100 ns dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 41 ns output delay time (2) t pd 1 , t pd 2 cl = 15 pf 1.2 s output delay time (3) t pd 3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation.
ST8011 v1.3 18/20 2004/09/08 (v ss = 0 v, v dd = +3.0 to +4.5 v, v 0 = + 6.0 to +15.0 v, t opr = -20 10+85 c) parameter symbol conditions min. typ. max. unit note shift clock period t w c k t r , t f w ckh 28 ns shift clock " l w ckl 28 ns data setup time t ds 20 ns data hold time t dh 23 ns latch pulse "h" pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 51 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns latch pulse fall to shift clock rise time t lsw 50 ns enable setup time t s 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 dispoff removal time t sd 100 ns dispoff "l" pulse width t wdl 1.2 ? d cl = 15 pf 57 n s output delay time (2) t pd 1 , t pd 2 cl = 15 pf 1.2 ? pd 3 cl = 15 pf 1.2 wck - t wckh - t wckl )/2 is maximum in the case of high speed operation.
ST8011 v1.3 19/20 2004/09/08 u timing chart of segment mode fr lp xdispoff seg 0 - seg 119 t pd1 t pd3 t pd2 fig. 8 timing characteristics (3) lp xck di4 - di0 xdispoff t wlph t ld t sl t lh t ls t wckh t f t r t wck t ds t dh top datalast data t wdl t sd t wckl
ST8011 v1.3 20/20 2004/09/08 the above information is the exclusive intellectual property of sitronix technology corp. and shall not be disclosed, distributed or reproduced without permission from sitronix.

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